Digital Low Level RF (LLRF) Control System

Digital LLRF systems for various machines like Indus-2, IR FEL at RRCAT have been developed and commissioned. Future proton accelerator having multiple accelerating structures will require RF systems at 325 MHz and 650 MHz with stringent RF field stability. To achieve this, design and development of pulsed digital LLRF systems at 325 MHz and 650 MHz is being done. Foreseeing the requirement of large numbers of LLRF systems, active mixer and I/Q based multichannel RF up down convertor boards and System on Chip FPGA (SoC-FPGA) based digital processing board is being developed. A simulator for 650 MHz super conducting RF cavity is developed in SIMULINK to test and optimize the LLRF system before its integration with SCRF cavity. For safe and healthy operation of RF systems, FPGA PXI based RF Power Detection and Protection System has been developed. This system consists of four RF power detection channels, four analog input channels and sixteen digital input channels to implement interlocks for protection of super conducting RF cavity and associated sub-systems. To achieve amplitude and phase stability of ± 0.1% and ± 0.1°, a test set-up has been developed in lab for characterization and qualification of RF components to be used in precision LLRF system.

Fig. 19: RF up down convertor board